1. Field of the Invention
The present invention relates to a step and repeat direct exposure system for repeatedly exposing a semiconductor wafer to a circuit or device pattern on a reticle. The invention also relates to such a system in which during the initial masking operation an alignment target is placed on the wafer at each circuit location. During subsequent masking operations, image alignment is achieved by viewing through the image exposure lens both the reticle alignment pattern and the virtual image of an alignment target on the wafer.
2. Description of the Prior Art
In the fabrication of integrated circuits and discrete semiconductor devices, many identical devices or circuits are formed simultaneously on a single semiconductor wafer. Typically the wafer is of silicon, and has a diameter on the order of three to five inches. Depending on the size of the device or circuit, upwards of fifty, a hundred or more such items may be formed on a single wafer. At the end of the fabrication process, the wafer is scribed and split to form separate dies each containing an individual device or circuit. These dies then are separately packaged to complete the fabrication.
Many successive process operations are carried out on each wafer. The number and type of such process steps will differ depending on the type of device that is being fabricated. For example, different process steps will be used to form circuits having bipolar transistors, metal gate field effect transistors, silicon gate field effect transistors, or C-MOS (complementary metal-oxide semiconductor) devices, to name but a few. Common to all of these processes, however, is the necessity for photographically defining specific areas within each circuit or device at which process operations occur. From as few as three to as many as twelve such photographic "masking" operations are carried out on each wafer during the fabrication process.
By way of example, consider a very simple metal gate field effect transistor (FET) fabrication process. Initially, the silicon wafer is covered with a relatively thick field oxide layer of silicon dioxide. This is covered with a light sensitive photoresist material which is exposed to light through a first photographic mask to define the regions at which the individual FET's are to be formed. The exposed and developed photoresist acts as a shield to allow selective etching away of the field oxide in the regions where FET's are to be made.
A thin gate oxide layer then is grown directly on the silicon substrate in these exposed regions. Another photoresist step employing a second photographic mask is used to define the locations of the source and drain of each FET. Openings are formed through the thin gate oxide layer at the locations defined by this source-drain mask. Dopant material is diffused through the openings to form the source and drain. This diffusion operation takes place at a high temperature, typically on the order of 1100 degrees C. Simultaneously oxide is grown to cover the source and drain openings.
Next, a third photographic mask is used to define the locations of the metal gate electrode, the metal contacts to the source and drain regions, and the bonding pad locations for each FET element.
Next, a thick vapor deposited oxide is grown over the entire device as a protective coating. Finally, a fourth photographic mask is used to define the locations at which the vapor deposited oxide will be removed to expose the bonding pads for the FET gate, source and drain. The oxide is etched away in these defined locations to expose the metal pad regions to which electrical contact wires subsequently will be bonded.
Thus in this simple example, four separate photographic masks are utilized. It is of utmost importance that each successive mask be properly aligned with the circuit or device patterns that were defined by the earlier masking steps. This alignment is critical to proper functioning of the completed device. For example, in the FET process just described, the positioning of the third mask used to define the location of the metal gate electrode is very critical. The gate region must be precisely located above the gate oxide between the source and drain openings. Misregistration could caused the gate electrode to overlap the source or drain, thereby degrading FET performance, or worse yet, causing a short circuit from the gate to the source or drain, thereby rendering the device inoperative.
The problem of mask misregistration becomes even more critical as the density of individual components in each integrated circuit increases. To form an integrated circuit having a large number of individual components requires that each of these components be extremely small. In today's integrated circuits, element spacings as small as 2 micrometers may be demanded. Such fine resolution places exceedingly close tolerance demands on the registration of successive photographic masks during the fabrication process. Indeed, the degree to which such successive registration can be achieved is one of the principle factors limiting the density or number of devices per square centimeter that can be achieved in large scale integrated circuits.
The illustrative process described above concerned the fabrication of a single FET device. In practice, multiple devices, or multiple circuits each of which includes many individual devices, are fabricated on a single wafer. To accomplish this in the past, each photographic mask constituted a glass plate containing multiple identical pattern images at locations corresponding to the plural devices or circuits being fabricated on a single wafer. For example, if fifty identical circuits are being formed on the wafer in five rows of ten circuits each, then each mask would contain fifty identical patterns, precisely arranged in the corresponding array of five rows and ten columns.
The actual photographic exposure of the wafer being processed is carried out in the following manner. The wafer is placed on a holder or stage which is situated under a binocular microscope. The mask or reticle itself (i.e., the glass plate with multiple photographic images on it) is mounted in a holder directly above the wafer, but below the microscope. An operator views both the mask and wafer through the microscope, and physically manipulates either the stage or the mask holder until alignment is achieved, as determined by visual inspection. A single high intensity light source then is used simultaneously to expose the entire wafer through the entire mask. That is, the wafer is exposed simultaneously to all of the individual patterns arrayed on the mask.
Certain alignment problems are inherent in this process. The first occurs in the fabrication of the mask itself. Normally this is done by repetitive exposure from enlarged artwork that contains the pattern for a single one (or possible a few) of the devices being fabricated on the wafer. This individual pattern is exposed successively into each array position on the mask. Positioning errors can occur. For example, one or more images may be slightly out of line or skewed with respect to the rows or columns of other images on the same mask. If this should happen, even if perfect registration were achieved between the wafer and every other mask used during device fabrication, the misregistration of certain patterns in this individual mask well may result in defective devices or circuits.
Even if perfect positioning of each individual image in the mask array can be achieved, misregistration still can occur during the exposure process. For example, the operator may align the mask with the wafer by using only one or two reference points near the center or near an edge of the wafer and mask. If the mask is slightly skewed with respect to the wafer, as for example if the mask were rotated very slightly so that its center line was not exactly parallel to the center line of the wafer, this error may not be noticed by the operator. For example, if the operator viewed the mask and wafer only near the center, within the limited field of vision of the microscope the mask and wafer may appear to be aligned. However, at the periphery of the wafer the mask may be offset by an amount which, though very small, may be enough to cause misregistration sufficient to impair device operation.
Another complication arises as a result of the thermal cycling of the wafer itself during certain process steps. For example, in the process described above the source and drain diffusion is carried out at very high temperature. Typically the wafer will be subjected to may such steps in which its temperature is changed from room temperature to a highly elevated temperature and then returned once again to room temperature. This thermal cycling may produce some irregular warping of the wafer itself. As a result, even if the photographic masks themselves are perfect, the image they produce on a warped wafer may be out of registration with the images formed during earlier process steps which were carried out before the wafer became warped.
Many of these misregistration problems are eliminated by a system in which a mask with multiple images is totally eliminated. Instead, a reticle containing a single pattern corresponding to one, or at most a very few, of the circuits or devices to be formed on a wafer is employed for direct exposure onto the wafer itself. That is, at each masking operation a single mask with multiple images is not used. Rather, the reticle with its single pattern is used repetitively and successively to expose, one at a time, all of the devices or circuits being formed on the wafer. In such a direct exposure system, the reticle is mounted in a projection camera that is situated above a stage holding the wafer. One device or circuit of the wafer is aligned under the camera, and the exposure for that circuit is made through the reticle. The wafer then is stepped to the next circuit location, for example by moving the stage appropriately in the row or column direction. The next circuit then is exposed through the reticle. The process is repeated for each of the multiple circuits or devices on the wafer.
This direct exposure, wafer stepping technique can totally eliminate the misregistation problems associated with forming a mask having mutiple images, and using that mask simultaneously to expose all of the circuits at once. It offers yet an additional advantage in that the size of the reticle used to expose the image can be much larger (e.g., five time or ten times larger) than the actual size of the circuit being formed. This is in contrast with the mutiple image mask technique in which the individual images have a one-to-one size relationship with the circuits or devices on the wafer. The use of such an enlarged pattern to make the exposure onto the wafer, through optical size reduction, offers the opportunity to produce image geometries of smaller dimensions then can be achieved through a one-to-one masking operation.
Certain problems are posed by a direct exposure, wafer stepping system. These relate principally to alignment of the reticle image with previously exposed patterns on the wafer. In prior art systems, only a single alignment was done for each masking operation, regardless of how many individual reticle exposures were made. A pair of alignment targets were placed on opposite sides of the wafer either prior to or during the inital masking operation. A high precision stage translation device, typically using a laser interferometer for motion control, then was used to step the wafer to each array position between successive exposures. At the next and each successive masking operation, an indirect off axis method was used initially to align the wafer with the new reticle.
To accomplish this, each reticle was provided with a pair of reference targets. Initially the reticle was manually aligned to a reference at an off-axis portion of the camera, using these reference targets. Next a wafer was placed on the wafer stage and separately aligned to the same off-axis reference in the camera. As successive individual exposures were made, proper positioning of the state depended on the accuracy of the mechanical X-Y drive system. No individual alignment of each circuit with respect to the camera and reticle is made, and none is possible. Such alignment depends entirely on the precision with which the stage can be controlled by its positioning system. Substantial opportunity exists for the introduction of positioning error.
An object of the present invention invention is to provide an improved direct exposure, step and repeat imaging system which overcomes the disadvantages of the prior art. Another objective of the present invention is to provide a direct exposure system in which alignment of the reticle and target is carried out through the camera optics. A further objective is to provide a system in which an individual alignment target may be provided at each separate circuit location on the wafer, and in which an individual alignment can be made at each array location before every exposure.
Still another object is to provide a direct exposure system which compensates for non-planar, warped or non-uniform thickness conditions of the wafer being exposed. In this regard, an object of the present invention is to provide a wafer platform and related mechanism for automatically bringing the surface portion of the wafer being exposed into parallel alignment with the bottom of the camera. This aids perfect focus even though the camera optics may have a shallow depth of field.
Yet another objective of the present invention is to provide a system for accurately prealigning the wafer on the stage both rotationally and along orthogonal axes. Such prealignment eliminates rotational positioning errors of the wafer, and aids in obtaining accurate stepping through the array.